library ieee;
use ieee.std_logic_1164.all;

entity fullAdder is
	port (
		ina : in bit;
		inb : in bit;
		cin : in bit;
		sum, cout : out bit
	);
end entity fullAdder;

architecture DATAFLOW of fullAdder is
	
	signal ab : bit;
	signal cina : bit;
	signal ab2 : bit;
	
begin

	sum <= ina xor inb xor cin; 
	cout <= (ina and inb) or (cin and (ina xor inb));

end architecture DATAFLOW;

